As means for converting the duty ratio of a PWM signal into voltage, a CR filter (capacitor-resistor integrating circuit) that is high in conversion accuracy and is low in cost is often used (see FIG. 2). However, the existing CR filters are not able to achieve both a good output voltage response at the time of a change in the duty ratio and a reduction of the ripple voltage that is contained in the output voltage.
A technology related to the invention will be described in detail. As shown in FIG. 2, a duty ratio/voltage conversion circuit 201 that includes a CR filter (CR integrating circuit) 200 further includes a first resistor 203, a capacitor 204, and a second resistor 205 as component elements. The second resistor 205 is a load resistor that is connected to a connecting point between the first resistor 203 and the capacitor 204. The resistance value of the first resistor 203 and the capacitance of the capacitor 204 are not related to the average value of the voltage that is output. The average value of the voltage output from an output terminal 207 depends only on the duty ratio of an input signal. Therefore, the duty ratio/voltage conversion circuit 201 is able to highly accurately convert the duty ratio into voltage. However, in the duty ratio/voltage conversion circuit 201, the response time during which the output voltage changes in the event of a change in the duty ratio of the input signal and a pulsating component (i.e., ripple, which depends on the input frequency) of the output voltage occurring in the same event contradict with each other, giving rise to a problem of the ripple being inconveniently large in a use where high response speed is required. That is, the problem is that the response time can be shortened by lessening a time constant τ, but that if the time constant τ is lessened, the amplitude of the ripple becomes large.
In Japanese Patent Application Publication No. 6-37641 (JP-A-6-37641), FIG. 1 discloses a pulse width/voltage conversion circuit that is capable of converting a PWM signal into a voltage signal whose ripple is small in amount. This pulse width/voltage conversion circuit includes a first CR integrating circuit that integrates the PWM signal, analog switch means connected to an output of the first CR integrating circuit, and a second CR integrating circuit that is connected to the first CR integrating circuit when the switch means is on. The switch means is turned off for a period of a high level of the PWM signal, and is turned on for a period of a low level of the PWM signal.
The pulse width/voltage conversion circuit outputs as a final converted voltage an average value of the voltage during the period of the low level of the PWM signal which is held by the second CR integrating circuit. However, the average voltage of the entire PWM signal (covering the period of the high level of the signal and the period of the low level of the signal) is greater than the average voltage during the low-level period. Therefore, this pulse width/voltage conversion circuit has a problem in which the duty ratio of the PWM signal cannot be directly reflected on the output voltage (i.e., there arises an error in comparison with the case where the duty ratio is directly reflected). The size of the error can be lessened by a certain degree by increasing the time constant of the first CR integrating circuit. However, this involves a problem in which the follow-up of the output voltage delays when the duty ratio of the PWM signal changes. Besides, when the duty ratio is 100% (continuously at the high level), another problem arises in which the output voltage of the second CR integrating circuit becomes unstable because of an input terminal thereof being open, while the output voltage of the first CR integration circuit becomes maximum. The other embodiments disclosed in Japanese Patent Application Publication No. 6-37641 (JP-A-6-37641) have substantially the same problems as described above, and also have a problem of increase of the number of component parts.